Impact of z14 on Processor Cache and MLC Expenses

Todd Havekost

By Todd Havekost

Expense reduction initiatives among IT organizations typically prioritize efforts to reduce IBM Monthly License Charge (MLC) software expense, which commonly represents the single largest line item in the mainframe budget.

On current (z13 and z14) mainframe processors, at least one-third and often more than one-half of all machine cycles are spent waiting for instructions and data to be staged into level one processor cache so that they can be executed. Since such a significant portion of CPU consumption is dependent on processor cache efficiency, awareness of your key cache metrics and the actions you can take to improve cache efficiency are both essential.

This is the final article in a four-part series focusing on this vital but often overlooked subject area. (You can read Article 1, Article 2, and Article 3.) This article examines the changes in processor cache design for the z14 processor model. The z14 reflects evolutionary changes in processor cache from the z13 in contrast to the revolutionary changes that occurred between the zEC12 and z13. The cache design changes for the z14 were particularly designed to help workloads that place high demands on processor cache. These “high RNI” workloads frequently experienced a negative impact when migrating from the zEC12 to z13.

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Optimizing MLC Software Costs with Processor Configurations

Todd Havekost

By Todd Havekost

This is the third article in a four-part series focusing largely on a topic that has the potential to generate significant cost savings, but which has not received the attention it deserves, namely processor cache optimization. (Read part one here and part two here.) Without an understanding of the vital role processor cache plays in CPU consumption and clear visibility into the key cache metrics in your environment, significant opportunities to reduce CPU consumption and MLC expense may not be realized.

This article highlights how optimizing physical hardware configurations can substantially improve processor cache efficiency and thus reduce MLC costs. Three approaches to maximizing work executing on Vertical High (VH) logical CPs through increasing the number of physical CPs will be considered. Restating one of the key findings of the first article, work executing on VHs optimizes processor cache effectiveness, because its 1-1 relationship with a physical CP means it will consistently access the same processor cache.

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zHyperLink: The Holy Grail of Mainframe I/O?

GilbertzHyperLink

By Gilbert Houtekamer, Ph.D.

Now that it has become harder and harder to make the processor faster, IBM is looking for other ways to make their mainframes perform better.

This has resulted in new co-processors for compression and encryption and now also, with the z14 processor, in a new technology called zHyperLink. This new I/O connectivity aims to significantly reduce the I/O response time, while at the same time not increase the processor (CP) load.

This new technology comes with a set of promises and restrictions that will cause you to rethink the design of your storage and replication infrastructure. The days of distance limitations are back, which has big implications for synchronous replication in particular.

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